Overview

The CD4013 (commonly CD4013BE in a 14-pin DIP package) is a classic high-voltage CMOS dual D-type flip-flop IC from the standard 4000B logic family. It contains two independent, identical D-type flip-flops, each equipped with Data (DD), Clock (CLKCLK), asynchronous Set (SETSET), asynchronous Reset (RESETRESET), true output (QQ), and complementary output (Q‾\overline{Q}).

Operating over a wide supply range from 3.0 V3.0\text{ V} to 18.0 V18.0\text{ V}, the CD4013 is extremely popular in DIY electronics for toggle switches (push-button ON/OFF latches), frequency division by 2 (connecting Q‾\overline{Q} back to DD), and digital control logic.

Quick reference

Logic FamilyHigh-Voltage CMOS (4000B Series)
Package14-Pin DIP (Through-Hole) / SOIC-14 / TSSOP-14
Supply Voltage Range (VDDV_{DD})3.0 V3.0\text{ V} to 18.0 V18.0\text{ V} DC
Flip-Flops2 Independent D-Type Flip-Flops
Max Clock Frequency12 MHz12\text{ MHz} at VDD=10VV_{DD} = 10\text{V}
Propagation Delay (tpdt_{pd})65 ns65\text{ ns} typical at VDD=10VV_{DD} = 10\text{V}
OutputsComplementary True (QQ) and Inverted (Q‾\overline{Q}) per stage

Pinout (14-Pin DIP Package)

text
        ┌──────────┐
     1Q ─│ 1     14 │─ VDD
    1~Q ─│ 2     13 │─ 2Q
   1CLK ─│ 3     12 │─ 2~Q
 1RESET ─│ 4     11 │─ 2CLK
     1D ─│ 5     10 │─ 2RESET
   1SET ─│ 6      9 │─ 2D
    VSS ─│ 7      8 │─ 2SET
        └──────────┘
PinNameDescription
11QFlip-Flop 1 True output
21~Q~Flip-Flop 1 Inverted output
31CLKFlip-Flop 1 Clock input (Positive-edge triggered)
41RESETFlip-Flop 1 Reset input (Asynchronous, active-HIGH)
51DFlip-Flop 1 Data input
61SETFlip-Flop 1 Set input (Asynchronous, active-HIGH)
7VSSGround reference (0 V)
82SETFlip-Flop 2 Set input (Asynchronous, active-HIGH)
92DFlip-Flop 2 Data input
102RESETFlip-Flop 2 Reset input (Asynchronous, active-HIGH)
112CLKFlip-Flop 2 Clock input (Positive-edge triggered)
122~Q~Flip-Flop 2 Inverted output
132QFlip-Flop 2 True output
14VDDPositive power supply (+3.0V to +18.0V DC)

Truth Table (Each Flip-Flop)

Clock (CLK)Data (D)Reset (RESET)Set (SET)Output (Q)Output (Q‾\overline{Q})
Low-to-High (↑\uparrow)Low (0)Low (0)Low (0)Low (0)High (1)
Low-to-High (↑\uparrow)High (1)Low (0)Low (0)High (1)Low (0)
Low or High (↓\downarrow)XLow (0)Low (0)UnchangedUnchanged
XXHigh (1)Low (0)Low (0)High (1)
XXLow (0)High (1)High (1)Low (0)
XXHigh (1)High (1)High (1)High (1)

Toggle Switch / Divide-by-2 Circuit

Connecting the inverted output (Q‾\overline{Q}) back to the Data input (DD) configures the flip-flop as a Toggle Flip-Flop (Divide-by-2):

text
                  ┌──────────────┐
                  │    CD4013    │
       Pulse ───> │ 3: 1CLK   1Q │ ───> Output Frequency (f_CLK / 2)
                  │              │
       ┌───────── │ 2: 1~Q   1D  │ <───┐
       │          └──────────────┘     │
       └───────────────────────────────┘

Common mistakes

  • Floating SET and RESET pins: Unlike 74HC series where reset inputs are often active-LOW, CD4013 Set and Reset inputs are active-HIGH. Leaving them floating will cause the flip-flop to latch into a constant reset or set state. Tie unused SET and RESET pins to VSS (GND).
  • No button debouncing on Clock input: Connecting a physical mechanical push-button directly to CLK will cause multiple clock edges due to contact bounce, making toggle switches skip states randomly. Add an RC filter or Schmitt trigger debouncer.

Notes

  • 4000B High Voltage Versatility: Supports up to 18V supplies directly, making it popular for 12V automotive and relay control circuits without needing 5V LDO regulators.

Assets & downloads