Overview

The 74HC139 (commonly SN74HC139N in a 16-pin DIP package) is a high-speed CMOS dual 2-to-4 line decoder / demultiplexer IC. It contains two completely independent 2-to-4 decoders, each featuring 2 address inputs (A0,A1A_0, A_1), an active-LOW Enable input (E‾\overline{E} / G‾\overline{G}), and 4 active-LOW outputs (Y‾0,Y‾1,Y‾2,Y‾3\overline{Y}_0, \overline{Y}_1, \overline{Y}_2, \overline{Y}_3).

When enabled (E‾=0\overline{E} = 0), the 2-bit binary address selects exactly one of the four outputs to pull LOW while keeping the remaining three outputs HIGH. The 74HC139 is widely used in microcontrollers, memory chip-select decoding, and signal demultiplexing.

Quick reference

Logic FamilyHigh-Speed CMOS (HC)
Package16-Pin DIP (Through-Hole) / SOIC-16 / TSSOP-16
Supply Voltage Range (VCCV_{CC})2.0 V2.0\text{ V} to 6.0 V6.0\text{ V} DC
Decoders per IC2 Independent 2-to-4 Line Decoders
Propagation Delay (tpdt_{pd})13 ns13\text{ ns} typical at VCC=4.5VV_{CC} = 4.5\text{V}
Enable ControlActive-LOW Enable (1E‾\overline{1E}, 2E‾\overline{2E})
OutputsActive-LOW Outputs (1Y0‾…1Y3‾\overline{1Y0} \dots \overline{1Y3}, 2Y0‾…2Y3‾\overline{2Y0} \dots \overline{2Y3})

Pinout (16-Pin DIP Package)

text
        ┌──────────────┐
    1~E~ ─│ 1         16 │─ VCC
    1A0 ─│ 2         15 │─ 2~E~
    1A1 ─│ 3         14 │─ 2A0
   1~Y0~ ─│ 4         13 │─ 2A1
   1~Y1~ ─│ 5         12 │─ 2~Y0~
   1~Y2~ ─│ 6         11 │─ 2~Y1~
   1~Y3~ ─│ 7         10 │─ 2~Y2~
    GND ─│ 8          9 │─ 2~Y3~
        └──────────────┘
PinNameDescription
11~E~ / 1~G~Decoder 1 Enable input (Active-LOW: LOW = Enabled, HIGH = Disables outputs)
21A0Decoder 1 Address bit 0 input
31A1Decoder 1 Address bit 1 input
4, 5, 6, 71~Y0~–1~Y3~Decoder 1 outputs (Active-LOW)
8GNDGround reference (0 V)
9, 10, 11, 122~Y3~–2~Y0~Decoder 2 outputs (Active-LOW)
132A1Decoder 2 Address bit 1 input
142A0Decoder 2 Address bit 0 input
152~E~ / 2~G~Decoder 2 Enable input (Active-LOW)
16VCCPower supply voltage input (+2.0V to +6.0V DC)

Function Table (Each Decoder)

Enable (E‾\overline{E})Address Bit 1 (A1A_1)Address Bit 0 (A0A_0)Y‾0\overline{Y}_0Y‾1\overline{Y}_1Y‾2\overline{Y}_2Y‾3\overline{Y}_3
High (1)XXHigh (1)High (1)High (1)High (1)
Low (0)Low (0)Low (0)Low (0)High (1)High (1)High (1)
Low (0)Low (0)High (1)High (1)Low (0)High (1)High (1)
Low (0)High (1)Low (0)High (1)High (1)Low (0)High (1)
Low (0)High (1)High (1)High (1)High (1)High (1)Low (0)

Specifications

ParameterSymbolMinTypMaxUnitConditions
Supply Voltage RangeVCCV_{CC}2.05.06.0VOperational range
Propagation Delay (A→YA \to Y)tpdt_{pd}—1325nsVCC=4.5V,CL=50pFV_{CC} = 4.5\text{V}, C_L = 50\text{pF}
Enable Propagation (E→YE \to Y)tent_{en}—1123nsVCC=4.5V,CL=50pFV_{CC} = 4.5\text{V}, C_L = 50\text{pF}
High-Level Output VoltsVOHV_{OH}4.44.5—VVCC=4.5V,IOH=−20μAV_{CC} = 4.5\text{V}, I_{OH} = -20\mu\text{A}
Low-Level Output VoltsVOLV_{OL}—0.10.4VVCC=4.5V,IOL=4mAV_{CC} = 4.5\text{V}, I_{OL} = 4\text{mA}

Common mistakes

  • Expecting active-HIGH outputs: Outputs (Y‾0…Y‾3\overline{Y}_0 \dots \overline{Y}_3) are active-LOW (they transition to 0V when selected). This is ideal for active-LOW Chip Select (CS‾\overline{CS}) pins on SPI flash/RAM memories.
  • Floating enable pins: Drive E‾\overline{E} LOW to enable decoding. Leaving E‾\overline{E} floating will cause inputs to be ignored and outputs to remain HIGH.

Notes

  • Cascading for 3-to-8 Decoding: Connecting the two halves of a 74HC139 together (using A2A_2 to invert enable inputs) creates a single 3-to-8 decoder, acting as a compact dual-package alternative to the 74HC138.

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