Overview

The CD4026 (commonly CD4026BE in a 16-pin DIP package) is a 5-stage Johnson decade counter IC with built-in 7-segment display output decoders, manufactured by Texas Instruments and ON Semiconductor. It converts clock pulses directly into active-HIGH signals to drive common-cathode 7-segment LED display digits without needing an intermediate BCD decoder IC (like the 74HC4511).

Operating across a supply voltage range of 3.0 V3.0\text{ V} to 18.0 V18.0\text{ V}, the CD4026 features Carry-Out (COUTCOUT) for multi-digit cascading, Display Enable (DEDE) for power saving, and active-HIGH Reset for clearing the count.

Quick reference

Counter Type5-Stage Johnson Decade Counter with 7-Segment Decoder
Package16-Pin DIP (Through-Hole) / SOIC-16 / TSSOP-16
Supply Voltage Range (VDDV_{DD})3.0 V3.0\text{ V} to 18.0 V18.0\text{ V} DC
Display SupportCommon-Cathode LED 7-Segment Displays (Direct Drive)
Max Clock Frequency5.0 MHz5.0\text{ MHz} typical at VDD=10VV_{DD} = 10\text{V}
Cascading OutputCarry-Out (COUTCOUT) divides clock by 10 for multi-digit counters
Control FunctionsClock Enable (CLK EN), Display Enable (DE), Reset (RESET)

Pinout (16-Pin DIP Package)

text
        ┌──────────────┐
    CLK ─│ 1         16 │─ VDD
 CLK EN ─│ 2         15 │─ RESET
     DE ─│ 3         14 │─ UNGATED C
    DEO ─│ 4         13 │─ e
   COUT ─│ 5         12 │─ c
      f ─│ 6         11 │─ b
      g ─│ 7         10 │─ a
    VSS ─│ 8          9 │─ d
        └──────────────┘
PinNameDescription
1CLKClock input pin (Increments counter on LOW-to-HIGH transition)
2CLK ENClock Enable input pin (Active-LOW: GND = Enabled, VDD = Disabled)
3DEDisplay Enable input pin (Active-HIGH: VDD = Display ON, GND = Outputs OFF)
4DEODisplay Enable Output (Used for blanking cascading display stages)
5COUTCarry-Out output pin (Pulses HIGH once every 10 clock cycles for next digit)
6, 7, 9, 10, 11, 12, 13a–gDecoded active-HIGH outputs driving segments a through g of LED display
8VSSGround reference (0 V)
14UNGATED CSegment c output unaffected by DE display blanking
15RESETAsynchronous Reset input pin (Active-HIGH: VDD = Resets count to 0)
16VDDPositive power supply input (+3.0V to +18.0V DC)

Decoded Segment Display Output Mapping

text
     ── a ──
    │       │
    f       b
    │── g ──│
    e       c
    │       │
     ── d ──
CountSegments Active (Active-HIGH = 1)Displayed Digit
0a, b, c, d, e, f0
1b, c1
2a, b, d, e, g2
3a, b, c, d, g3
4b, c, f, g4
5a, c, d, f, g5
6a, c, d, e, f, g6
7a, b, c7
8a, b, c, d, e, f, g8
9a, b, c, d, f, g9

Multi-Digit Cascade Wiring

text
   Clock Signal ───> [Digit 1: CD4026] ─── (COUT Pin 5) ───> [Digit 2: CD4026 (CLK Pin 1)]
                           │                                          │
                  [Segments a-g Out]                         [Segments a-g Out]
                           │                                          │
                 Common-Cathode Digit 1                    Common-Cathode Digit 2

Common mistakes

  • Connecting to Common-Anode Displays: CD4026 outputs are active-HIGH (source current). They work directly with Common-Cathode displays. They will NOT drive Common-Anode displays properly without inverters.
  • Floating CLK EN or RESET pins: CLK EN is active-LOW (tie to GND for normal counting); RESET is active-HIGH (tie to GND for normal counting). Leaving either floating will prevent counting.

Notes

  • CD4026 vs CD4033: The CD4026 features Display Enable controls (DE/DEO), whereas the CD4033 features Ripple Blanking (RBI/RBO) for zero-suppression in multi-digit displays.

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