74HC244 — Octal Non-Inverting Buffer / Line Driver with 3-State Outputs

Overview

The 74HC244 (SN74HC244 / 74HCT244) is an industry-standard high-speed silicon-gate CMOS octal non-inverting buffer / line driver IC manufactured by Texas Instruments, Nexperia, and onsemi. Housed in a 20-pin through-hole DIP-20 and surface-mount SOIC-20 / TSSOP-20 package, it is organized as two independent 4-bit buffer banks, each controlled by its own active-LOW output enable pin ( $1\bar{OE}$ and $2\bar{OE}$ ).

Operating across a supply voltage range of $2.0\text{V}$ to $6.0\text{V}$ DC with a rapid propagation delay of $9\text{ ns}$ at $5\text{V}$ , the 74HC244 provides high-current 3-state drive capability ( $\pm 6.0\text{ mA}$ , driving up to 15 LSTTL loads). It is universally employed in retrocomputing systems, embedded microcontroller boards, and hardware programmer adapters (such as ByteBlaster, AVR-ISP parallel port programmers, and logic analyzer pods) for bus buffering, memory address/data line driving, and bidirectional bus isolation.

Quick reference


Logic Family	High-Speed CMOS (74HC) / TTL-Compatible (74HCT)
Function	Octal Non-Inverting Buffer / Line Driver (3-State)
Bus Architecture	Two 4-Bit Non-Inverting Groups with Independent Enables
Package	20-pin DIP (DIP-20 / PDIP-20) / 20-pin SOIC / TSSOP-20
Supply Voltage ( $V_{CC}$ )	$2.0\text{ V}$ to $6.0\text{ V}$ (74HC) / $4.5\text{ V} \dots 5.5\text{ V}$ (74HCT)
Propagation Delay ( $t_{pd}$ )	$9\text{ ns}$ typ ( $18\text{ ns}$ max) at $V_{CC} = 5.0\text{ V}$
Output Drive Current ( $I_{OH}/I_{OL}$ )	$\pm 6.0\text{ mA}$ at $5.0\text{ V}$ (15 LSTTL loads)
Controls	Dual Active-LOW Output Enables ( $1\bar{OE}$ on Pin 1, $2\bar{OE}$ on Pin 19)
Inverting Twin	74HC240 (Octal Inverting Buffer)

Pinout (DIP-20 Package)

text

                            ┌───┴───┐
       (Active-Low) 1/OE   1│ 1   20│ VCC (+2V to +6V)
       (Bank 1, In)  1A0   2│       │19 2/OE (Active-Low)
       (Bank 2, Out) 2Y0   3│ 74HC  │18 1Y0 (Bank 1, Out)
       (Bank 1, In)  1A1   4│  244  │17 2A0 (Bank 2, In)
       (Bank 2, Out) 2Y1   5│ DIP-20│16 1Y1 (Bank 1, Out)
       (Bank 1, In)  1A2   6│       │15 2A1 (Bank 2, In)
       (Bank 2, Out) 2Y2   7│       │14 1Y2 (Bank 1, Out)
       (Bank 1, In)  1A3   8│       │13 2A2 (Bank 2, In)
       (Bank 2, Out) 2Y3   9│       │12 1Y3 (Bank 1, Out)
                     GND  10│       │11 2A3 (Bank 2, In)
                            └───────┘

Pin	Name	Type	Description
1	`1/OE`	Control Input	Bank 1 Active-LOW Output Enable (Tie to GND to enable $1Y_0 \dots 1Y_3$ )
2, 4, 6, 8	`1A0 - 1A3`	Data Inputs	Bank 1 Data Inputs
3, 5, 7, 9	`2Y0 - 2Y3`	Data Outputs	Bank 2 Non-Inverting 3-State Outputs
10	`GND`	Power	Common Ground reference ( $0\text{ V}$ )
11, 13, 15, 17	`2A3 - 2A0`	Data Inputs	Bank 2 Data Inputs
12, 14, 16, 18	`1Y3 - 1Y0`	Data Outputs	Bank 1 Non-Inverting 3-State Outputs
19	`2/OE`	Control Input	Bank 2 Active-LOW Output Enable (Tie to GND to enable $2Y_0 \dots 2Y_3$ )
20	`VCC`	Power	Positive Supply Voltage ( $+2.0\text{ V}$ to $+6.0\text{ V}$ )

Function / Truth Table (Each 4-Bit Bank)

Output Enable ( $\bar{OE}$ )	Data Input ( $A$ )	Output ( $Y$ )	Output State
L	L	L	Active Non-Inverting ( $Y = A$ )
L	H	H	Active Non-Inverting ( $Y = A$ )
H	X	Z	High Impedance (Disabled / Disconnected)

Comparison: 74HC244 vs 74HC541 vs 74HC245

Parameter	74HC244	74HC541	74HC245
Function	Octal Buffer	Octal Buffer	Octal Bus Transceiver
Directionality	Unidirectional (Dual 4-Bit)	Unidirectional (8-Bit)	Bidirectional ( $A \leftrightarrow B$ )
Pinout Style	Staggered	Flow-Through (Clean Layout)	Flow-Through
Control Pins	$1\bar{OE}, 2\bar{OE}$	$\bar{OE}_1, \bar{OE}_2$	$\bar{OE}, \text{DIR}$

Common mistakes

Leaving Output Enable pins floating: If $1\bar{OE}$ or $2\bar{OE}$ is left unconnected, floating charges will randomly place the corresponding 4-bit output group into high-impedance (Z) mode. Connect enable pins to GND for continuous buffering.
Tracing confusion due to staggered pinout: Note that Pins 2, 4, 6, 8 are Inputs for Bank 1, but adjacent Pins 3, 5, 7, 9 are Outputs for Bank 2. (For a clean flow-through layout with inputs on one side and outputs on the other, consider the 74HC541).

Notes

74HCT244 Level Shifting: Operating a 74HCT244 at $V_{CC} = 5.0\text{V}$ provides effortless $3.3\text{V} \to 5.0\text{V}$ unidirectional level translation because its minimum high-level input threshold is only $V_{IH} = 2.0\text{V}$ .